ugh
This commit is contained in:
RaphProductions
parent
f27e0a240c
commit
287a7fb312
3 changed files with 162 additions and 150 deletions
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@ -60,10 +60,10 @@ program_t *elf_load(char *data) {
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uint64_t offset = phdr[i].p_offset;
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uint64_t flags = VMM_PRESENT;
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if (phdr[i].p_flags & PF_W)
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//if (phdr[i].p_flags & PF_W)
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flags |= VMM_WRITABLE;
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if (!(phdr[i].p_flags & PF_X))
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flags |= VMM_NX;
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//if (!(phdr[i].p_flags & PF_X))
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// flags |= VMM_NX;
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flags |= VMM_USER;
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@ -1,23 +1,23 @@
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#include "mm/vmm.h"
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#include "limine.h"
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#include "mm/pmm.h"
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#include "mm/memop.h"
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#include "mm/pmm.h"
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#include "sys/log.h"
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#include "vmm.h"
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#include <stddef.h>
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__attribute__((
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used,
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section(
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".limine_requests"))) static volatile struct limine_paging_mode_request
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pmrq = {.id = LIMINE_PAGING_MODE_REQUEST,
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.revision = 3,
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.mode = LIMINE_PAGING_MODE_X86_64_4LVL};
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__attribute__((used, section(".limine_requests")))
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static volatile struct limine_paging_mode_request pmrq = {
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.id = LIMINE_PAGING_MODE_REQUEST,
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.revision = 3,
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.mode = LIMINE_PAGING_MODE_X86_64_4LVL
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};
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__attribute__((used, section(".limine_requests")))
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static volatile struct limine_executable_address_request karq = {
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.id = LIMINE_EXECUTABLE_ADDRESS_REQUEST,
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.revision = 0,
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__attribute__((used, section(".limine_requests"))) static volatile struct
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limine_executable_address_request karq = {
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.id = LIMINE_EXECUTABLE_ADDRESS_REQUEST,
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.revision = 0,
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};
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pagemap_t *vmm_kernel_pm = NULL;
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@ -25,179 +25,184 @@ pagemap_t *vmm_current_pm = NULL;
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int vmm_kernel_pm_exists = 0;
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pagemap_t *vmm_alloc_pm() {
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pagemap_t *pm = (pagemap_t*)HIGHER_HALF((uint64_t)pmm_request_page());
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memset(pm, 0, PMM_PAGE_SIZE);
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pagemap_t *pm = (pagemap_t *)HIGHER_HALF((uint64_t)pmm_request_page());
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memset(pm, 0, PMM_PAGE_SIZE);
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/*if (vmm_kernel_pm_exists) {
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pm->toplevel = (uint64_t*)HIGHER_HALF((uint64_t)pmm_request_page());
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memset(pm->toplevel, 0, PMM_PAGE_SIZE);
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/*if (vmm_kernel_pm_exists) {
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pm->toplevel = (uint64_t*)HIGHER_HALF((uint64_t)pmm_request_page());
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memset(pm->toplevel, 0, PMM_PAGE_SIZE);
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for (int i = 256; i < 512; i++) {
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pm->toplevel[i] = vmm_kernel_pm->toplevel[i];
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}
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} else {
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for (int i = 256; i < 512; i++) {
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pm->toplevel[i] = vmm_kernel_pm->toplevel[i];
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}
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} else {
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__asm__ volatile("mov %%cr3, %0" : "=r"(pm->toplevel) : : "memory");
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pm->toplevel = HIGHER_HALF(pm->toplevel);
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logln(info, "vmm", "Limine-provided kernel PML4: %p", pm->toplevel);
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__asm__ volatile("mov %%cr3, %0" : "=r"(pm->toplevel) : : "memory");
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pm->toplevel = HIGHER_HALF(pm->toplevel);
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logln(info, "vmm", "Limine-provided kernel PML4: %p", pm->toplevel);
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}*/
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}*/
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pm->toplevel = (uint64_t *)HIGHER_HALF((uint64_t)pmm_request_page());
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memset(pm->toplevel, 0, PMM_PAGE_SIZE);
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pm->toplevel = (uint64_t*)HIGHER_HALF((uint64_t)pmm_request_page());
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memset(pm->toplevel, 0, PMM_PAGE_SIZE);
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if (vmm_kernel_pm_exists) {
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for (int i = 256; i < 512; i++) {
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pm->toplevel[i] = vmm_kernel_pm->toplevel[i];
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}
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if (vmm_kernel_pm_exists) {
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for (int i = 256; i < 512; i++) {
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pm->toplevel[i] = vmm_kernel_pm->toplevel[i];
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}
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}
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return pm;
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return pm;
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}
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void vmm_release_pm(pagemap_t *pm) {
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memset(pm->toplevel, 0, PMM_PAGE_SIZE);
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memset(pm, 0, PMM_PAGE_SIZE);
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pmm_free_page(pm->toplevel);
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pmm_free_page(pm);
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memset(pm->toplevel, 0, PMM_PAGE_SIZE);
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memset(pm, 0, PMM_PAGE_SIZE);
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pmm_free_page(pm->toplevel);
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pmm_free_page(pm);
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}
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void vmm_sanity_check() {
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uint64_t *my_memory = pmm_request_page();
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*my_memory = 0x40;
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uint64_t *my_memory = pmm_request_page();
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*my_memory = 0x40;
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pagemap_t *pm = vmm_alloc_pm();
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vmm_map(pm, 0x1000, (uint64_t)my_memory, VMM_PRESENT | VMM_WRITABLE);
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pagemap_t *pm = vmm_alloc_pm();
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vmm_map(pm, 0x1000, (uint64_t)my_memory, VMM_PRESENT | VMM_WRITABLE);
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uint64_t *my_ptr = (uint64_t*)0x1000;
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uint64_t ptr_val = 0;
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vmm_load_pagemap(pm);
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ptr_val = *my_ptr;
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vmm_load_pagemap(vmm_kernel_pm);
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uint64_t *my_ptr = (uint64_t *)0x1000;
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uint64_t ptr_val = 0;
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vmm_load_pagemap(pm);
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ptr_val = *my_ptr;
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vmm_load_pagemap(vmm_kernel_pm);
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if (ptr_val != 0x40) {
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log("vmm - sanity check failed. system halted.\n");
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asm("cli");
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while (1)
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asm("hlt");
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}
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if (ptr_val != 0x40) {
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log("vmm - sanity check failed. system halted.\n");
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asm("cli");
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while (1)
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asm("hlt");
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}
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}
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void vmm_init() {
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if (pmrq.response->mode != LIMINE_PAGING_MODE_X86_64_4LVL) {
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log("vmm - Soaplin only supports 4-level paging!\n");
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asm("cli; hlt;");
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}
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vmm_kernel_pm = vmm_alloc_pm();
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vmm_kernel_pm_exists = 1;
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if (pmrq.response->mode != LIMINE_PAGING_MODE_X86_64_4LVL) {
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log("vmm - Soaplin only supports 4-level paging!\n");
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asm("cli; hlt;");
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}
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vmm_kernel_pm = vmm_alloc_pm();
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vmm_kernel_pm_exists = 1;
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uint64_t kphysaddr = karq.response->physical_base;
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uint64_t kvirtaddr = karq.response->virtual_base;
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uint64_t kphysaddr = karq.response->physical_base;
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uint64_t kvirtaddr = karq.response->virtual_base;
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uint64_t reqs_start = ALIGN_DOWN((uint64_t)reqs_start_ld, PMM_PAGE_SIZE);
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uint64_t reqs_end = ALIGN_UP((uint64_t)reqs_end_ld, PMM_PAGE_SIZE);
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uint64_t text_start = ALIGN_DOWN((uint64_t)text_start_ld, PMM_PAGE_SIZE);
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uint64_t text_end = ALIGN_UP((uint64_t)text_end_ld, PMM_PAGE_SIZE);
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uint64_t rodata_start = ALIGN_DOWN((uint64_t)rodata_start_ld, PMM_PAGE_SIZE);
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uint64_t rodata_end = ALIGN_UP((uint64_t)rodata_end_ld, PMM_PAGE_SIZE);
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uint64_t data_start = ALIGN_DOWN((uint64_t)data_start_ld, PMM_PAGE_SIZE);
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uint64_t data_end = ALIGN_UP((uint64_t)data_end_ld, PMM_PAGE_SIZE);
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uint64_t reqs_start = ALIGN_DOWN((uint64_t)reqs_start_ld, PMM_PAGE_SIZE);
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uint64_t reqs_end = ALIGN_UP((uint64_t)reqs_end_ld, PMM_PAGE_SIZE);
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uint64_t text_start = ALIGN_DOWN((uint64_t)text_start_ld, PMM_PAGE_SIZE);
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uint64_t text_end = ALIGN_UP((uint64_t)text_end_ld, PMM_PAGE_SIZE);
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uint64_t rodata_start = ALIGN_DOWN((uint64_t)rodata_start_ld, PMM_PAGE_SIZE);
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uint64_t rodata_end = ALIGN_UP((uint64_t)rodata_end_ld, PMM_PAGE_SIZE);
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uint64_t data_start = ALIGN_DOWN((uint64_t)data_start_ld, PMM_PAGE_SIZE);
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uint64_t data_end = ALIGN_UP((uint64_t)data_end_ld, PMM_PAGE_SIZE);
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log("vmm - mapping .requests section...\n");
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for (uint64_t req = reqs_start; req < reqs_end; req += PMM_PAGE_SIZE) {
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vmm_map(vmm_kernel_pm, req, req - kvirtaddr + kphysaddr,
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VMM_PRESENT | VMM_WRITABLE);
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}
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log("vmm - mapping .requests section...\n");
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for (uint64_t req = reqs_start; req < reqs_end; req += PMM_PAGE_SIZE) {
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vmm_map(vmm_kernel_pm, req, req - kvirtaddr + kphysaddr, VMM_PRESENT | VMM_WRITABLE);
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}
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log("vmm - mapping .text section...\n");
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for (uint64_t text = text_start; text < text_end; text += PMM_PAGE_SIZE) {
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vmm_map(vmm_kernel_pm, text, text - kvirtaddr + kphysaddr, VMM_PRESENT);
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}
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log("vmm - mapping .text section...\n");
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for (uint64_t text = text_start; text < text_end; text += PMM_PAGE_SIZE) {
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vmm_map(vmm_kernel_pm, text, text - kvirtaddr + kphysaddr, VMM_PRESENT);
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}
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log("vmm - mapping .rodata section...\n");
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for (uint64_t roData = rodata_start; roData < rodata_end;
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roData += PMM_PAGE_SIZE)
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vmm_map(vmm_kernel_pm, roData, roData - kvirtaddr + kphysaddr,
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VMM_PRESENT | VMM_NX);
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log("vmm - mapping .rodata section...\n");
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for (uint64_t roData = rodata_start; roData < rodata_end; roData += PMM_PAGE_SIZE)
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vmm_map(vmm_kernel_pm, roData, roData - kvirtaddr + kphysaddr,
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VMM_PRESENT | VMM_NX);
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log("vmm - mapping .data section...\n");
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for (uint64_t data = data_start; data < data_end; data += PMM_PAGE_SIZE)
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vmm_map(vmm_kernel_pm, data, data - kvirtaddr + kphysaddr,
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VMM_PRESENT | VMM_WRITABLE | VMM_NX);
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log("vmm - mapping .data section...\n");
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for (uint64_t data = data_start; data < data_end; data += PMM_PAGE_SIZE)
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vmm_map(vmm_kernel_pm, data, data - kvirtaddr + kphysaddr,
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VMM_PRESENT | VMM_WRITABLE | VMM_NX);
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log("vmm - mapping address from 0x0 to 0x100000000...\n");
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for (uint64_t gb4 = 0; gb4 < 0x100000000; gb4 += PMM_PAGE_SIZE) {
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vmm_map(vmm_kernel_pm, gb4, gb4, VMM_PRESENT | VMM_WRITABLE);
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vmm_map(vmm_kernel_pm, (uint64_t)HIGHER_HALF(gb4), gb4,
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VMM_PRESENT | VMM_WRITABLE);
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}
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log("vmm - mapping address from 0x0 to 0x100000000...\n");
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for (uint64_t gb4 = 0; gb4 < 0x100000000; gb4 += PMM_PAGE_SIZE) {
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vmm_map(vmm_kernel_pm, gb4, gb4, VMM_PRESENT | VMM_WRITABLE);
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vmm_map(vmm_kernel_pm, (uint64_t)HIGHER_HALF(gb4), gb4, VMM_PRESENT | VMM_WRITABLE);
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}
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vmm_load_pagemap(vmm_kernel_pm);
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vmm_load_pagemap(vmm_kernel_pm);
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vmm_sanity_check();
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log("vmm - initialized!\n");
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vmm_sanity_check();
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log("vmm - initialized!\n");
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}
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void vmm_load_pagemap(pagemap_t *pm) {
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if (!pm)
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return;
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if (!pm)
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return;
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if (!pm->toplevel)
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return;
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if (!pm->toplevel)
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return;
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vmm_current_pm = pm;
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__asm__ volatile("mov %0, %%cr3" : : "r"(PHYSICAL(pm->toplevel)) : "memory");
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vmm_current_pm = pm;
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__asm__ volatile("mov %0, %%cr3" : : "r"(PHYSICAL(pm->toplevel)) : "memory");
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}
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static uint64_t *__vmm_get_next_lvl(uint64_t *level, uint64_t entry, uint64_t flags) {
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(void)flags;
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if (!(level[entry] & 1)){
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uint64_t *pml = HIGHER_HALF(pmm_request_page());
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memset(pml, 0, PMM_PAGE_SIZE);
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level[entry] = ((uint64_t)PHYSICAL(pml) & 0x000FFFFFFFFFF000ULL) | 0b111;
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}
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return HIGHER_HALF(PTE_GET_ADDR(level[entry]));
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static uint64_t *__vmm_get_next_lvl(uint64_t *level, uint64_t entry,
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uint64_t flags) {
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if (!(level[entry] & 1)) {
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uint64_t *pml = HIGHER_HALF(pmm_request_page());
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memset(pml, 0, PMM_PAGE_SIZE);
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level[entry] = (uint64_t)PHYSICAL(pml);
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}
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level[entry] |= (flags & 0xFFF); // N'ajoute que les flags pertinents
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return HIGHER_HALF(PTE_GET_ADDR(level[entry]));
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}
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uint64_t vmm_get_flags(pagemap_t* pm, uint64_t vaddr) {
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uint64_t pml4_entry = (vaddr >> 39) & 0x1ff;
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uint64_t pml3_entry = (vaddr >> 30) & 0x1ff;
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uint64_t pml2_entry = (vaddr >> 21) & 0x1ff;
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uint64_t pml1_entry = (vaddr >> 12) & 0x1ff;
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uint64_t vmm_get_flags(pagemap_t *pm, uint64_t vaddr) {
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uint64_t pml4_entry = (vaddr >> 39) & 0x1ff;
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uint64_t pml3_entry = (vaddr >> 30) & 0x1ff;
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uint64_t pml2_entry = (vaddr >> 21) & 0x1ff;
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uint64_t pml1_entry = (vaddr >> 12) & 0x1ff;
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uint64_t *pml3 = __vmm_get_next_lvl(pm->toplevel, pml4_entry, 0);
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uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_entry, 0);
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uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_entry, 0);
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uint64_t *pml3 = __vmm_get_next_lvl(pm->toplevel, pml4_entry, 0);
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uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_entry, 0);
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uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_entry, 0);
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return pml1[pml1_entry] & 0x7000000000000FFF;
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return pml1[pml1_entry] & 0x7000000000000FFF;
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}
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uint64_t virt_to_phys(pagemap_t *pagemap, uint64_t virt)
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{
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uint64_t pml4_idx = (virt >> 39) & 0x1FF;
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uint64_t pml3_idx = (virt >> 30) & 0x1FF;
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uint64_t pml2_idx = (virt >> 21) & 0x1FF;
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uint64_t pml1_idx = (virt >> 12) & 0x1FF;
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uint64_t virt_to_phys(pagemap_t *pagemap, uint64_t virt) {
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uint64_t pml4_idx = (virt >> 39) & 0x1FF;
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uint64_t pml3_idx = (virt >> 30) & 0x1FF;
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uint64_t pml2_idx = (virt >> 21) & 0x1FF;
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uint64_t pml1_idx = (virt >> 12) & 0x1FF;
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uint64_t *pml3 = __vmm_get_next_lvl(pagemap->toplevel, pml4_idx, 0);
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uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_idx, 0);
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uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_idx, 0);
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uint64_t *pml3 = __vmm_get_next_lvl(pagemap->toplevel, pml4_idx, 0);
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uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_idx, 0);
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uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_idx, 0);
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uint64_t phys_addr = pml1[pml1_idx] & 0x000FFFFFFFFFF000; // Masque pour obtenir l'adresse physique (en retirant les bits de flags)
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uint64_t phys_addr =
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pml1[pml1_idx] &
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0x000FFFFFFFFFF000; // Masque pour obtenir l'adresse physique (en retirant
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// les bits de flags)
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return phys_addr;
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return phys_addr;
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}
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void vmm_map(pagemap_t *pm, uint64_t vaddr, uint64_t paddr, uint64_t flags) {
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uint64_t pml4_entry = (vaddr >> 39) & 0x1ff;
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uint64_t pml3_entry = (vaddr >> 30) & 0x1ff;
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uint64_t pml2_entry = (vaddr >> 21) & 0x1ff;
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uint64_t pml1_entry = (vaddr >> 12) & 0x1ff;
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uint64_t pml4_entry = (vaddr >> 39) & 0x1ff;
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uint64_t pml3_entry = (vaddr >> 30) & 0x1ff;
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uint64_t pml2_entry = (vaddr >> 21) & 0x1ff;
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uint64_t pml1_entry = (vaddr >> 12) & 0x1ff;
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uint64_t *pml3 = __vmm_get_next_lvl(pm->toplevel, pml4_entry, flags);
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uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_entry, flags);
|
||||
uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_entry, flags);
|
||||
uint64_t *pml3 = __vmm_get_next_lvl(pm->toplevel, pml4_entry, flags);
|
||||
uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_entry, flags);
|
||||
uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_entry, flags);
|
||||
|
||||
pml1[pml1_entry] = paddr | flags;
|
||||
pml1[pml1_entry] = paddr | flags;
|
||||
}
|
||||
void vmm_unmap(pagemap_t *pm, uint64_t vaddr) {
|
||||
uint64_t pml1_entry = (vaddr >> 12) & 0x1ff;
|
||||
|
|
@ -206,13 +211,16 @@ void vmm_unmap(pagemap_t *pm, uint64_t vaddr) {
|
|||
uint64_t pml4_entry = (vaddr >> 39) & 0x1ff;
|
||||
|
||||
uint64_t *pml3 = __vmm_get_next_lvl(pm->toplevel, pml4_entry, 0);
|
||||
if (pml3 == NULL) return;
|
||||
if (pml3 == NULL)
|
||||
return;
|
||||
uint64_t *pml2 = __vmm_get_next_lvl(pml3, pml3_entry, 0);
|
||||
if (pml2 == NULL) return;
|
||||
if (pml2 == NULL)
|
||||
return;
|
||||
uint64_t *pml1 = __vmm_get_next_lvl(pml2, pml2_entry, 0);
|
||||
if (pml1 == NULL) return;
|
||||
if (pml1 == NULL)
|
||||
return;
|
||||
|
||||
pml1[pml1_entry] = 0;
|
||||
|
||||
__asm__ volatile ("invlpg (%0)" : : "b"(vaddr) : "memory");
|
||||
__asm__ volatile("invlpg (%0)" : : "b"(vaddr) : "memory");
|
||||
}
|
||||
|
|
@ -150,5 +150,9 @@ void schedule(registers_t *regs)
|
|||
memcpy(regs, &curr_proc->regs, sizeof(registers_t));
|
||||
|
||||
// Finally, load our pagemap
|
||||
vmm_load_pagemap(curr_proc->pm);
|
||||
//if (memcmp(curr_proc->name, "Init", 4)== 0) {
|
||||
vmm_load_pagemap(curr_proc->pm);
|
||||
//asm("cli");
|
||||
//while (1)
|
||||
// asm("hlt");}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue