Added TrueType base and HDA driver
This commit is contained in:
Jozef Nagy
parent
aa3f734406
commit
42cc0d9f40
GPG key ID:
459A4811CEAC7068
30 changed files with 7120 additions and 35 deletions
289
boot/platform/uefi/drivers/intel-hda/pciconf.c
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289
boot/platform/uefi/drivers/intel-hda/pciconf.c
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@ -0,0 +1,289 @@
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/*********************************************************************************/
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/* Module Name: pciconf.h */
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/* Project: AurixOS */
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/* */
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/* Copyright (c) 2018-2025, Rafael Rodrigues Machado, Jozef Nagy */
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/* All rights reserved. */
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/* This program and the accompanying materials are licensed and made available */
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/* under the terms and conditions of the BSD License which accompanies */
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/* this distribution. The full text of the license may be found at */
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/* http://opensource.org/licenses/bsd-license. */
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/* */
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/* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, */
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/* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. */
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/*********************************************************************************/
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#include <lib/string.h>
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#include <mm/mman.h>
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#include <efi.h>
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#include <efilib.h>
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#include <print.h>
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#include <hda.h>
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#include <pciconf.h>
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#include <stdint.h>
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#include <stddef.h>
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EFI_PCI_IO_PROTOCOL *HdaPciIoProtocol = NULL;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgePciIoProtocol = NULL;
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EFI_STATUS TearDownCommonBuffer(uint8_t *HostAddress,
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uint64_t Length,
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void *Mapping)
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{
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EFI_STATUS Status;
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Status = HdaPciIoProtocol->Unmap(HdaPciIoProtocol, Mapping);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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Status = HdaPciIoProtocol->FreeBuffer(HdaPciIoProtocol, EFI_SIZE_TO_PAGES(Length), (void *)HostAddress);
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return Status;
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}
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EFI_STATUS ReleaseHdaPciIoHandler()
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{
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EFI_STATUS Status = EFI_SUCCESS;
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// TODO
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/*
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Status = TearDownCommonBuffer((uint8_t *)CorbAddress, 1024, CorbMapping);
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if (!EFI_ERROR(Status)) {
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Status = TearDownCommonBuffer((uint8_t *)RirbAddress, 2048, RirbMapping);
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}
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*/
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return Status;
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}
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EFI_STATUS SetupCommonBuffer(uint8_t **HostAddress,
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uint64_t Length,
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void **Mapping,
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uint64_t Alignment)
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{
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(void)Mapping;
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(void)Alignment;
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*HostAddress = mem_alloc(Length);
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return EFI_SUCCESS;
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}
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EFI_STATUS GetHdaPciIoHandler()
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{
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EFI_HANDLE *DetectedHandles = NULL;
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EFI_UINTN DetectedHandlesCount = 0;
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EFI_UINTN CurrentHandle = 0;
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EFI_STATUS Status = EFI_SUCCESS;
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EFI_GUID PciIoProtocolGuid = EFI_PCI_IO_PROTOCOL_GUID;
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EFI_UINTN SegmentNumber;
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EFI_UINTN BusNumber;
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EFI_UINTN DeviceNumber;
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EFI_UINTN FunctionNumber;
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if (HdaPciIoProtocol == NULL) {
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Status = gBootServices->LocateHandleBuffer(ByProtocol,
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&PciIoProtocolGuid,
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NULL,
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&DetectedHandlesCount,
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&DetectedHandles);
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if (!EFI_ERROR(Status)) {
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for (CurrentHandle = 0; CurrentHandle < DetectedHandlesCount; CurrentHandle++) {
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Status = gBootServices->OpenProtocol(DetectedHandles[CurrentHandle],
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&PciIoProtocolGuid,
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(VOID**) &HdaPciIoProtocol,
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gImageHandle,
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NULL,
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EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL);
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Status = HdaPciIoProtocol->GetLocation(HdaPciIoProtocol,
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&SegmentNumber,
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&BusNumber,
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&DeviceNumber,
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&FunctionNumber);
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debug("GetHdaPciIoHandler(): Found device %llu:%llu:%llu\n", SegmentNumber, BusNumber, DeviceNumber, FunctionNumber);
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// This means a HDA controller was detected
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if (BusNumber == HDA_BUS && DeviceNumber == HDA_DEV && FunctionNumber == HDA_FUNC) {
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debug("Handle detected\r\n");
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return EFI_SUCCESS;
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}
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gBootServices->CloseProtocol(DetectedHandles[CurrentHandle],
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&PciIoProtocolGuid,
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gImageHandle,
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NULL);
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}
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}
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}
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return EFI_NOT_FOUND;
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}
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EFI_STATUS GetRootBridgeIoHandler()
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{
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EFI_UINTN handleCount = 0;
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EFI_HANDLE *DetectedHandles = NULL;
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EFI_STATUS Status = EFI_SUCCESS;
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EFI_GUID PciRootBridgeIoProtocolGuid = EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID;
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if (RootBridgePciIoProtocol == NULL) {
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Status = gBootServices->LocateHandleBuffer(ByProtocol,
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&PciRootBridgeIoProtocolGuid,
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NULL,
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&handleCount,
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&DetectedHandles);
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if (!EFI_ERROR(Status)) {
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Status = gBootServices->OpenProtocol(DetectedHandles[0],
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&PciRootBridgeIoProtocolGuid,
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(void **)&RootBridgePciIoProtocol,
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gImageHandle,
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NULL,
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EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL);
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}
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}
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return Status;
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}
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EFI_STATUS GetControllerRegisterSet(PCI_HDA_REGION *PcieDeviceConfigSpace,
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HDA_CONTROLLER_REGISTER_SET *ControllerRegisterSet)
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{
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uint64_t IssCount = 0;
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uint64_t OssCount = 0;
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uint64_t BssCount = 0;
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uint64_t HdaControllerBar = (PcieDeviceConfigSpace->HDBARL & 0xFFFFFFF0);
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RootBridgePciIoProtocol->Mem.Read(RootBridgePciIoProtocol, EfiPciWidthUint8, HdaControllerBar, sizeof(HDA_CONTROLLER_REGISTER_SET) / sizeof(uint8_t), (void *)ControllerRegisterSet);
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IssCount = HDA_ISS_COUNT(ControllerRegisterSet->GCAP);
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OssCount = HDA_OSS_COUNT(ControllerRegisterSet->GCAP);
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BssCount = HDA_BSS_COUNT(ControllerRegisterSet->GCAP);
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if (IssCount > 0) {
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ControllerRegisterSet->ISS = mem_alloc(IssCount * sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR));
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memset(ControllerRegisterSet->ISS, 0, IssCount * sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR));
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RootBridgePciIoProtocol->Mem.Read(RootBridgePciIoProtocol, EfiPciWidthUint8, HdaControllerBar + CALCULATE_ISSN_OFFSET(0), (sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR) * IssCount) / sizeof(uint8_t), (void *)ControllerRegisterSet->ISS);
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}
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if (OssCount > 0) {
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ControllerRegisterSet->OSS = mem_alloc(OssCount * sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR));
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memset(ControllerRegisterSet->OSS, 0, OssCount * sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR));
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RootBridgePciIoProtocol->Mem.Read(RootBridgePciIoProtocol, EfiPciWidthUint8, HdaControllerBar + CALCULATE_OSSN_OFFSET(0, ControllerRegisterSet->GCAP), (sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR) * OssCount) / sizeof(uint8_t), (void *)ControllerRegisterSet->OSS);
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}
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if (BssCount > 0) {
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ControllerRegisterSet->BSS = mem_alloc(BssCount * sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR));
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RootBridgePciIoProtocol->Mem.Read(RootBridgePciIoProtocol, EfiPciWidthUint8, HdaControllerBar + CALCULATE_BSSN_OFFSET(0, ControllerRegisterSet->GCAP), (sizeof(HDA_CONTROLLER_STREAM_DESCRIPTOR) * BssCount) / sizeof(uint8_t), (void *)ControllerRegisterSet->BSS);
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS WritePciMemory(uint64_t Address,
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void *Value,
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uint64_t Count,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width)
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{
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return RootBridgePciIoProtocol->Mem.Write(RootBridgePciIoProtocol, Width, Address, Count, Value);
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}
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EFI_STATUS ReadPciMemory(uint64_t Address,
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void *Value,
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uint64_t Count,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width)
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{
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return RootBridgePciIoProtocol->Mem.Read(RootBridgePciIoProtocol, Width, Address, Count, Value);
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}
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EFI_STATUS WriteControllerRegister(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint64_t Offset,
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void *Value,
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uint64_t Count,
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uint8_t BarIndex,
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EFI_PCI_IO_PROTOCOL_WIDTH Width)
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{
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(void)PcieDeviceConfigSpace;
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EFI_STATUS Status = EFI_SUCCESS;
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EFI_UINTN VariableWidth = 0;
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switch (Width) {
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case EfiPciWidthUint32:
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VariableWidth = sizeof(uint32_t);
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break;
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case EfiPciWidthUint16:
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VariableWidth = sizeof(uint16_t);
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break;
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case EfiPciWidthUint8:
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VariableWidth = sizeof(uint8_t);
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break;
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default:
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return EFI_INVALID_PARAMETER;
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}
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void *ReadValue = mem_alloc(VariableWidth);
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memset(ReadValue, 0, VariableWidth);
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HdaPciIoProtocol->Mem.Write(HdaPciIoProtocol, Width, BarIndex, Offset, Count, Value);
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Status = HdaPciIoProtocol->Mem.Read(HdaPciIoProtocol, Width, BarIndex, Offset, Count, ReadValue);
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mem_free(ReadValue);
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return Status;
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}
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EFI_STATUS ReadControllerRegister(PCI_HDA_REGION *PcieDeviceConfigSpace,
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EFI_UINT64 Offset,
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void *Value,
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EFI_UINTN Count,
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EFI_PCI_IO_PROTOCOL_WIDTH Width)
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{
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EFI_UINT64 HdaControllerBar = (PcieDeviceConfigSpace->HDBARL & 0xFFFFFFF0);
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return RootBridgePciIoProtocol->Mem.Read(RootBridgePciIoProtocol, (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, HdaControllerBar + Offset, Count, Value);
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}
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EFI_STATUS ReadControllerPcieConfiguration(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint64_t Offset,
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void *Value,
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uint64_t Count,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width)
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{
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EFI_UINT64 Address = (HDA_BUS << 24) | (HDA_DEV << 16) | (HDA_FUNC << 8) | Offset;
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return RootBridgePciIoProtocol->Pci.Read(RootBridgePciIoProtocol, Width, Address, Count, Value);
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}
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EFI_STATUS WriteControllerPcieConfiguration(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint64_t Offset,
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void *Value,
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uint64_t Count,
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width)
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{
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EFI_UINT64 Address = (HDA_BUS << 24) | (HDA_DEV << 16) | (HDA_FUNC << 8) | Offset;
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return RootBridgePciIoProtocol->Pci.Write(RootBridgePciIoProtocol, Width, Address, Count, Value);
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}
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EFI_STATUS GetPcieConfigSpace(EFI_UINTN Bus,
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EFI_UINTN Device,
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EFI_UINTN Function,
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PCI_HDA_REGION *PcieDeviceConfigSpace)
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{
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EFI_STATUS Status;
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if (PcieDeviceConfigSpace == NULL) {
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debug("PcieDeviceConfigSpace==NULL\n");
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}
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debug("Width=%u\n", (sizeof(PCI_HDA_REGION) / sizeof(uint8_t)));
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Status = RootBridgePciIoProtocol->Pci.Read(RootBridgePciIoProtocol, EfiPciIoWidthUint8,
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EFI_PCI_ADDRESS(Bus, Device, Function, 0),
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sizeof(PCI_HDA_REGION) / sizeof(EFI_UINT8),
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(void *)PcieDeviceConfigSpace);
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if (EFI_ERROR(Status)) {
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debug("GetPcieConfigSpace(): %s (%x)\n", efi_status_to_str(Status), Status);
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}
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return Status;
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}
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