Added TrueType base and HDA driver
This commit is contained in:
Jozef Nagy
parent
aa3f734406
commit
42cc0d9f40
GPG key ID:
459A4811CEAC7068
30 changed files with 7120 additions and 35 deletions
571
boot/platform/uefi/drivers/intel-hda/hda.c
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571
boot/platform/uefi/drivers/intel-hda/hda.c
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@ -0,0 +1,571 @@
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/*********************************************************************************/
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/* Module Name: hda.c */
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/* Project: AurixOS */
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/* */
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/* Copyright (c) 2018-2025, Rafael Rodrigues Machado, Jozef Nagy */
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/* All rights reserved. */
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/* This program and the accompanying materials are licensed and made available */
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/* under the terms and conditions of the BSD License which accompanies */
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/* this distribution. The full text of the license may be found at */
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/* http://opensource.org/licenses/bsd-license. */
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/* */
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/* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, */
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/* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. */
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/*********************************************************************************/
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#include <lib/string.h>
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#include <mm/mman.h>
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#include <efi.h>
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#include <efilib.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <print.h>
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#include <hda.h>
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#include <pciconf.h>
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// Number of rows that are updated by the timer event for debug purposes
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#define REFRESH_ROWS 9
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#define Bar0 0
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static uint64_t CorbCommandCount = 0;
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PCI_HDA_REGION *PcieDeviceConfigSpace;
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uint64_t *DmaPositionBuffer = NULL;
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uint64_t *AddressBSL = NULL;
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int16_t *AudioBuffer = NULL;
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uint64_t CorbAddress;
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void *CorbMapping = NULL;
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uint8_t CorbLastAddedCommandIndex = 0;
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uint64_t RirbAddress;
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void *RirbMapping = NULL;
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uint8_t RirbLastProcessedResponseIndex = 0;
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EFI_STATUS AddCommandToCorb(uint32_t VerbToSend)
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{
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CorbLastAddedCommandIndex += 1;
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if (CorbLastAddedCommandIndex >= 256) {
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CorbLastAddedCommandIndex = 0;
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}
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WritePciMemory(CorbAddress + (CorbLastAddedCommandIndex * sizeof(uint32_t)), (void *)&VerbToSend, 1, EfiPciWidthUint32);
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBWP, (void *)&CorbLastAddedCommandIndex, 1, Bar0, EfiPciWidthUint32);
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CorbCommandCount += 1;
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return EFI_SUCCESS;
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}
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EFI_STATUS ReadResponseFromRirb(uint64_t *VerbResponse)
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{
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RirbLastProcessedResponseIndex += 1;
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if (RirbLastProcessedResponseIndex >= 256) {
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RirbLastProcessedResponseIndex = 0;
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}
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return ReadPciMemory(RirbAddress + (RirbLastProcessedResponseIndex * sizeof(uint64_t)), VerbResponse, 1, EfiPciWidthUint64);
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}
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EFI_STATUS InitHda()
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{
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EFI_STATUS Status = EFI_SUCCESS;
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Status = GetHdaPciIoHandler();
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if (EFI_ERROR(Status))
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return Status;
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Status = GetRootBridgeIoHandler();
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if (EFI_ERROR(Status))
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return Status;
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return EFI_SUCCESS;
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}
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EFI_STATUS DisposeHdaLib()
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{
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// TODO: Release CORB and RIRB
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// Close protocols
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// Free Variables
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// Close events
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return EFI_SUCCESS;
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}
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EFI_STATUS AllocateCORBBuffer(PCI_HDA_REGION* PcieDeviceConfigSpace)
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{
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uint8_t *CorbAddressPointer = NULL;
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uint32_t ReadValue32 = 0;
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uint32_t WriteValue = 0;
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uint8_t WriteValue8 = 0;
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SetupCommonBuffer(&CorbAddressPointer, 1024, &CorbMapping, 16);
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CorbAddress = (uint64_t)CorbAddressPointer;
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WriteValue = (CorbAddress & 0xFFFFFFFF);
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBLBASE,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue = (CorbAddress >> 32);
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBUBASE,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue = 0;
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBWP,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue = 0x8000;
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBRP,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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ReadControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBRP,
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(void *)&ReadValue32, 1, EfiPciWidthUint32);
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WriteValue = 0;
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBRP,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue8 = 0x3;
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_CORBCTL,
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(void *)&WriteValue8, 1, Bar0, EfiPciWidthUint8);
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//debug("AllocateCORBBuffer(): CorbAddress=0x%llx\n", CorbAddress);
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//debug("AllocateCORBBuffer(): CorbMapping=0x%llx\n", CorbMapping);
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return EFI_SUCCESS;
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}
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EFI_STATUS AllocateRIRBBuffer(PCI_HDA_REGION* PcieDeviceConfigSpace)
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{
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uint8_t *RirbAddressPointer = NULL;
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uint32_t WriteValue = 0;
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uint8_t WriteValue8 = 0;
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SetupCommonBuffer(&RirbAddressPointer, 2048, &RirbMapping, 16);
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RirbAddress = (uint64_t)RirbAddressPointer;
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WriteValue = (RirbAddress & 0xFFFFFFFF);
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_RIRBLBASE,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue = (RirbAddress >> 32);
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_RIRBUBASE,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue = 0;
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_RIRBWP,
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(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
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WriteValue8 = 0x2;
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WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_RIRBCTL,
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(void *)&WriteValue8, 1, Bar0, EfiPciWidthUint8);
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//debug("AllocateRIRBBuffer(): RirbAddress=0x%llx\n", RirbAddress);
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//debug("AllocateRIRBBuffer(): RirbMapping=0x%llx\n", RirbMapping);
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return EFI_SUCCESS;
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}
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EFI_STATUS FillCodecNode(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint32_t CurrentNodeId,
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HDA_NODE_TYPE NodeType,
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struct Node *CurrentNode)
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{
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uint32_t CurrentSubordinateNodeCount = 0;
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struct Node TempNode;
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TempNode.NodeId = CurrentNodeId;
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TempNode.NodeType = NodeType;
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_VENDOR_ID, &TempNode.VendorId);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_REVISION_ID, &TempNode.RevisionId);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_SUBORDINATE_NODE_COUNT, &CurrentSubordinateNodeCount);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_FUNCTION_GROUP_TYPE, &TempNode.FunctionGroupType);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_AUDIO_FUNC_CAP, &TempNode.FuncCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_AUDIO_WIDGET_CAP, &TempNode.WidgetCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_SAMPLE_SIZE_RATE_CAP, &TempNode.SampleSizeRateCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_STREAM_FORMATS, &TempNode.StreamFormat);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_PIN_CAP, &TempNode.PinCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_INPUT_AMP_CAP, &TempNode.InputAmpCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_OUTPUT_AMP_CAP, &TempNode.OutputAmpCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_CONNECTION_LIST_LENGTH, &TempNode.ConnectionListLength);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_SUPPORTED_POWER_STATES, &TempNode.SupportedPowerStates);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_PROCESSING_CAP, &TempNode.ProcessingCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_GPIO_COUNT, &TempNode.GPIOCount);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_PARAMETER, HDA_PARAM_VOLUME_KNOB_CAP, &TempNode.VolKnobCap);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_POWER_STATE, 0, &TempNode.PowerState);
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentNodeId, HDA_VRB_GET_CHANNEL_STREAM_ID, 0, &TempNode.ChannelStreamId);
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TempNode.StartingChildNodeAddess = HDA_SUB_NODE_COUNT_START_NODE(CurrentSubordinateNodeCount);
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TempNode.SubordinateNodeCount = HDA_SUB_NODE_COUNT_TOTAL_NODE(CurrentSubordinateNodeCount);
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TempNode.WidgetType = HDA_WIDGET_TYPE(TempNode.WidgetCap);
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TempNode.RightGain = GetAmplifierGain(PcieDeviceConfigSpace, TempNode.NodeId, true, false);
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TempNode.LeftGain = GetAmplifierGain(PcieDeviceConfigSpace, TempNode.NodeId, true, true);
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memcpy(CurrentNode, &TempNode, sizeof(struct Node));
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return EFI_SUCCESS;
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}
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EFI_STATUS GetNodeById(struct Node *RootNode,
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uint32_t NodeIdToSearch,
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struct Node *NodeDetected)
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{
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struct Node *CurrentFunctionGroupNode = NULL;
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struct Node *CurrentWidgetNode = NULL;
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uint32_t CurrentFunctionGroupId = 0;
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uint32_t CurrentFgArrayIndexer = 0;
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uint32_t CurrentWidgetId = 0;
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uint32_t CurrentWidgetArrayIndexer = 0;
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for (CurrentFunctionGroupId = RootNode->StartingChildNodeAddess; CurrentFunctionGroupId < RootNode->StartingChildNodeAddess + RootNode->SubordinateNodeCount; CurrentFunctionGroupId++, CurrentFgArrayIndexer++) {
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CurrentFunctionGroupNode = &(RootNode->ChildNodes[CurrentFgArrayIndexer]);
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if (CurrentFunctionGroupNode->NodeId == NodeIdToSearch) {
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memcpy(NodeDetected, CurrentFunctionGroupNode, sizeof(struct Node));
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return EFI_SUCCESS;
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}
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CurrentWidgetArrayIndexer = 0;
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for (CurrentWidgetId = CurrentFunctionGroupNode->StartingChildNodeAddess; CurrentWidgetId < CurrentFunctionGroupNode->StartingChildNodeAddess + CurrentFunctionGroupNode->SubordinateNodeCount - 1; CurrentWidgetId++, CurrentWidgetArrayIndexer++) {
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CurrentWidgetNode = &(CurrentFunctionGroupNode->ChildNodes[CurrentWidgetArrayIndexer]);
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if (CurrentWidgetNode->NodeId == NodeIdToSearch) {
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memcpy(NodeDetected, CurrentWidgetNode,sizeof(struct Node));
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return EFI_SUCCESS;
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}
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}
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS GetCodecTree(PCI_HDA_REGION *PcieDeviceConfigSpace,
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struct Node *RootNode)
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{
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struct Node *CurrentFunctionGroupNode = NULL;
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struct Node *CurrentWidgetNode = NULL;
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uint32_t CurrentFunctionGroupId = 0;
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uint32_t CurrentFgArrayIndexer = 0;
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uint32_t CurrentWidgetId = 0;
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uint32_t CurrentWidgetArrayIndexer = 0;
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FillCodecNode(PcieDeviceConfigSpace, 0, HDA_NODE_ROOT, RootNode);
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RootNode->ChildNodes = mem_alloc(sizeof(struct Node) * (RootNode->SubordinateNodeCount - RootNode->StartingChildNodeAddess));
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memset(RootNode->ChildNodes, 0, sizeof(struct Node) * (RootNode->SubordinateNodeCount - RootNode->StartingChildNodeAddess));
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for (CurrentFunctionGroupId = RootNode->StartingChildNodeAddess; CurrentFunctionGroupId < RootNode->StartingChildNodeAddess + RootNode->SubordinateNodeCount; CurrentFunctionGroupId++, CurrentFgArrayIndexer++) {
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CurrentFunctionGroupNode = &(RootNode->ChildNodes[CurrentFgArrayIndexer]);
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FillCodecNode(PcieDeviceConfigSpace, CurrentFunctionGroupId, HDA_NODE_FUNCTION_GROUP, CurrentFunctionGroupNode);
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CurrentFunctionGroupNode->ChildNodes = mem_alloc(sizeof(struct Node) * CurrentFunctionGroupNode->StartingChildNodeAddess + CurrentFunctionGroupNode->SubordinateNodeCount);
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memset(CurrentFunctionGroupNode->ChildNodes, 0, sizeof(struct Node) * CurrentFunctionGroupNode->StartingChildNodeAddess + CurrentFunctionGroupNode->SubordinateNodeCount);
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CurrentWidgetArrayIndexer = 0;
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for (CurrentWidgetId = CurrentFunctionGroupNode->StartingChildNodeAddess; CurrentWidgetId < CurrentFunctionGroupNode->StartingChildNodeAddess + CurrentFunctionGroupNode->SubordinateNodeCount - 1; CurrentWidgetId++, CurrentWidgetArrayIndexer++) {
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CurrentWidgetNode = &(CurrentFunctionGroupNode->ChildNodes[CurrentWidgetArrayIndexer]);
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FillCodecNode(PcieDeviceConfigSpace, CurrentWidgetId, HDA_NODE_WIDGET, CurrentWidgetNode);
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}
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS ReleaseCodecTree(PCI_HDA_REGION *PcieDeviceConfigSpace,
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struct Node *RootNode)
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{
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struct Node *CurrentFunctionGroupNode = NULL;
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uint32_t CurrentFunctionGroupId = 0;
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uint32_t CurrentFgArrayIndexer = 0;
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for (CurrentFunctionGroupId = RootNode->StartingChildNodeAddess; CurrentFunctionGroupId < RootNode->StartingChildNodeAddess + RootNode->SubordinateNodeCount - 1; CurrentFunctionGroupId++, CurrentFgArrayIndexer++) {
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CurrentFunctionGroupNode = &(RootNode->ChildNodes[CurrentFgArrayIndexer]);
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mem_free(CurrentFunctionGroupNode->ChildNodes);
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}
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mem_free(RootNode->ChildNodes);
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return EFI_SUCCESS;
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}
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EFI_STATUS GetCodecData8BitPayload(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint8_t CodecAddress, uint8_t NodeId,
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HDA_VERB Verb, uint8_t VerbPayload,
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uint32_t *Response)
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{
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return EFI_SUCCESS;
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}
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EFI_STATUS GetCodecData8BitPayloadCorbRirb(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint8_t CodecAddress, uint8_t NodeId,
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HDA_VERB Verb, uint8_t VerbPayload,
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uint32_t *Response)
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{
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HDA_COMMAND_FIELD_8BIT_PAYLOAD Command;
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HDA_RESPONSE_FIELD *RawResponse;
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uint32_t VerbToSend = 0;
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uint64_t TempResponse = 0;
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Command.CAd = CodecAddress;
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Command.NID = NodeId;
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Command.VerbIdent = Verb;
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Command.VerbPayload = VerbPayload;
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memcpy(&VerbToSend, &Command, sizeof(uint32_t));
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AddCommandToCorb(VerbToSend);
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gBootServices->Stall(200);
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ReadResponseFromRirb(&TempResponse);
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RawResponse = (HDA_RESPONSE_FIELD *)&TempResponse;
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memcpy(Response, &RawResponse->Response, sizeof(uint32_t));
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return EFI_SUCCESS;
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}
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EFI_STATUS GetCodecData16BitPayloadCorbRirb(PCI_HDA_REGION *PcieDeviceConfigSpace,
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uint8_t CodecAddress, uint8_t NodeId,
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HDA_VERB Verb, uint16_t VerbPayload,
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uint32_t *Response)
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{
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HDA_COMMAND_FIELD_16BIT_PAYLOAD Command;
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HDA_RESPONSE_FIELD *RawResponse;
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uint32_t VerbToSend = 0;
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uint64_t TempResponse = 0;
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Command.CAd = CodecAddress;
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Command.NID = NodeId;
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Command.VerbIdent = Verb;
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Command.VerbPayload = VerbPayload;
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memcpy(&VerbToSend, &Command, sizeof(uint32_t));
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AddCommandToCorb(VerbToSend);
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gBootServices->Stall(200);
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ReadResponseFromRirb(&TempResponse);
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RawResponse = (HDA_RESPONSE_FIELD *)&TempResponse;
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memcpy(Response, &RawResponse->Response, sizeof(uint32_t));
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return EFI_SUCCESS;
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}
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EFI_STATUS SendCommandToAllWidgets8BitPayload (
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PCI_HDA_REGION *PcieDeviceConfigSpace,
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HDA_VERB Verb, uint8_t VerbPayload)
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{
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struct Node RootNode;
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uint32_t Response;
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GetCodecTree(PcieDeviceConfigSpace, &RootNode);
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struct Node *CurrentFunctionGroupNode = NULL;
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struct Node *CurrentWidgetNode = NULL;
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uint32_t CurrentFunctionGroupId = 0;
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uint32_t CurrentFgArrayIndexer = 0;
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uint32_t CurrentWidgetId = 0;
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uint32_t CurrentWidgetArrayIndexer = 0;
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, 0, Verb, VerbPayload, &Response);
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debug("Verb 0x%llx with payload 0x%llx sent to node 0x0\n", Verb, VerbPayload);
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for (CurrentFunctionGroupId = RootNode.StartingChildNodeAddess; CurrentFunctionGroupId < RootNode.StartingChildNodeAddess + RootNode.SubordinateNodeCount; CurrentFunctionGroupId++, CurrentFgArrayIndexer++) {
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GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentFunctionGroupId, Verb, VerbPayload, &Response);
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CurrentFunctionGroupNode = &(RootNode.ChildNodes[CurrentFgArrayIndexer]);
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CurrentWidgetArrayIndexer = 0;
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for (CurrentWidgetId = CurrentFunctionGroupNode->StartingChildNodeAddess; CurrentWidgetId < CurrentFunctionGroupNode->StartingChildNodeAddess + CurrentFunctionGroupNode->SubordinateNodeCount - 1; CurrentWidgetId++, CurrentWidgetArrayIndexer++) {
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CurrentWidgetNode = &(CurrentFunctionGroupNode->ChildNodes[CurrentWidgetArrayIndexer]);
|
||||
GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentWidgetId, Verb, VerbPayload, &Response);
|
||||
}
|
||||
}
|
||||
|
||||
ReleaseCodecTree(PcieDeviceConfigSpace, &RootNode);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS SendCommandToAllWidgets16BitPayload (
|
||||
PCI_HDA_REGION* PcieDeviceConfigSpace,
|
||||
HDA_VERB Verb, uint16_t VerbPayload)
|
||||
{
|
||||
struct Node RootNode;
|
||||
uint32_t Response;
|
||||
|
||||
GetCodecTree(PcieDeviceConfigSpace, &RootNode);
|
||||
|
||||
struct Node *CurrentFunctionGroupNode = NULL;
|
||||
struct Node *CurrentWidgetNode = NULL;
|
||||
|
||||
uint32_t CurrentFunctionGroupId = 0;
|
||||
uint32_t CurrentFgArrayIndexer = 0;
|
||||
|
||||
uint32_t CurrentWidgetId = 0;
|
||||
uint32_t CurrentWidgetArrayIndexer = 0;
|
||||
|
||||
GetCodecData16BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, 0, Verb, VerbPayload, &Response);
|
||||
|
||||
for (CurrentFunctionGroupId = RootNode.StartingChildNodeAddess; CurrentFunctionGroupId < RootNode.StartingChildNodeAddess + RootNode.SubordinateNodeCount; CurrentFunctionGroupId++, CurrentFgArrayIndexer++) {
|
||||
GetCodecData16BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentFunctionGroupId, Verb, VerbPayload, &Response);
|
||||
CurrentFunctionGroupNode = &(RootNode.ChildNodes[CurrentFgArrayIndexer]);
|
||||
CurrentWidgetArrayIndexer = 0;
|
||||
|
||||
for (CurrentWidgetId = CurrentFunctionGroupNode->StartingChildNodeAddess; CurrentWidgetId < CurrentFunctionGroupNode->StartingChildNodeAddess + CurrentFunctionGroupNode->SubordinateNodeCount - 1; CurrentWidgetId++, CurrentWidgetArrayIndexer++) {
|
||||
CurrentWidgetNode = &(CurrentFunctionGroupNode->ChildNodes[CurrentWidgetArrayIndexer]);
|
||||
GetCodecData16BitPayloadCorbRirb(PcieDeviceConfigSpace, 0, CurrentWidgetId, Verb, VerbPayload, &Response);
|
||||
}
|
||||
}
|
||||
|
||||
ReleaseCodecTree(PcieDeviceConfigSpace, &RootNode);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS GetCodecData16BitPayload(PCI_HDA_REGION* PcieDeviceConfigSpace,
|
||||
uint8_t CodecAddress, uint8_t NodeId,
|
||||
HDA_VERB Verb, uint16_t VerbPayload,
|
||||
uint32_t *Response)
|
||||
{
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
uint32_t GetAmplifierGain(PCI_HDA_REGION *PcieDeviceConfigSpace,
|
||||
uint8_t NodeId, bool InputOutput,
|
||||
bool LeftRight)
|
||||
{
|
||||
uint32_t Response = 0;
|
||||
uint16_t PayloadToSend = 0;
|
||||
|
||||
PayloadToSend = NodeId;
|
||||
PayloadToSend |= (InputOutput << 15);
|
||||
PayloadToSend |= (LeftRight << 13);
|
||||
|
||||
GetCodecData8BitPayloadCorbRirb(PcieDeviceConfigSpace, 0x0, NodeId, HDA_VRB_GET_AMPLIFIER_GAIN_MUTE, 0x0, &Response);
|
||||
return Response;
|
||||
}
|
||||
|
||||
EFI_STATUS DisablePcieInterrupts(PCI_HDA_REGION *PcieDeviceConfigSpace)
|
||||
{
|
||||
uint16_t CommandRegister = 0;
|
||||
|
||||
ReadControllerPcieConfiguration(PcieDeviceConfigSpace, HDA_OFFSET_PCIE_PCICMD, &CommandRegister, 1, EfiPciWidthUint16);
|
||||
CommandRegister += (1 << 10);
|
||||
WriteControllerPcieConfiguration(PcieDeviceConfigSpace, HDA_OFFSET_PCIE_PCICMD, (void *)&CommandRegister, 1, EfiPciWidthUint16);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS EnablePcieNoSnoop(PCI_HDA_REGION *PcieDeviceConfigSpace)
|
||||
{
|
||||
uint16_t DeviceControlRegister = 0;
|
||||
|
||||
ReadControllerPcieConfiguration(PcieDeviceConfigSpace, HDA_OFFSET_PCIE_DEVCTL, (void *)&DeviceControlRegister, 1, EfiPciWidthUint16);
|
||||
DeviceControlRegister += (1 << 11);
|
||||
WriteControllerPcieConfiguration(PcieDeviceConfigSpace, HDA_OFFSET_PCIE_DEVCTL, (void *)&DeviceControlRegister, 1, EfiPciWidthUint16);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS AddDescriptorListEntryOss0(PCI_HDA_REGION *PcieDeviceConfigSpace,
|
||||
HDA_CONTROLLER_REGISTER_SET *ControllerRegisterSet,
|
||||
uint64_t DataAddress,
|
||||
uint32_t DataLength,
|
||||
uint8_t BdlEntryIndex,
|
||||
uint32_t SdxLastValidIndex)
|
||||
{
|
||||
EFI_UINT64 BdlAddress;
|
||||
EFI_UINT32 BdlLower;
|
||||
EFI_UINT64 BdlUpper;
|
||||
|
||||
HDA_BUFFER_DESCRIPTOR_LIST *DescriptorList = NULL;
|
||||
|
||||
ReadControllerRegister(PcieDeviceConfigSpace, CALCULATE_OSSN_OFFSET(0, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXBDPL,
|
||||
(void *)&BdlLower, 1, EfiPciWidthUint32);
|
||||
ReadControllerRegister(PcieDeviceConfigSpace, CALCULATE_OSSN_OFFSET(0, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXBDPU,
|
||||
(void *)&BdlUpper, 1, EfiPciWidthUint32);
|
||||
|
||||
BdlAddress = BdlLower | (BdlUpper << 32);
|
||||
|
||||
DescriptorList = (HDA_BUFFER_DESCRIPTOR_LIST *)BdlAddress;
|
||||
DescriptorList->BDLEntry[BdlEntryIndex].Address = DataAddress;
|
||||
DescriptorList->BDLEntry[BdlEntryIndex].Length = DataLength;
|
||||
|
||||
// TODO: Enable this after Corb/Rirb start to process unsolicited responses
|
||||
DescriptorList->BDLEntry[BdlEntryIndex].IntrptOnComp = 1;
|
||||
|
||||
return WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_OSSN_OFFSET(0, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXLVI,
|
||||
(void *)&SdxLastValidIndex, 1, Bar0, EfiPciWidthUint32);
|
||||
}
|
||||
|
||||
EFI_STATUS AllocateStreamsPages(PCI_HDA_REGION *PcieDeviceConfigSpace,
|
||||
HDA_CONTROLLER_REGISTER_SET *ControllerRegisterSet)
|
||||
{
|
||||
uint8_t *BdlAddressPointer = NULL;
|
||||
void *BdlMapping = NULL;
|
||||
uint64_t BdlAddress;
|
||||
|
||||
// DMAPositionBuffer
|
||||
uint8_t *DmaAddressPointer = NULL;
|
||||
void *DmaMapping = NULL;
|
||||
uint64_t DmaAddress;
|
||||
|
||||
uint32_t WriteValue = 0;
|
||||
|
||||
uint64_t IssCount = (ControllerRegisterSet->GCAP >> 8) & 0xF;
|
||||
uint64_t OssCount = (ControllerRegisterSet->GCAP >> 12) & 0xF;
|
||||
uint64_t BssCount = (ControllerRegisterSet->GCAP >> 3) & 0x1F;
|
||||
uint64_t Count = 0;
|
||||
|
||||
for (Count = 0; Count < IssCount; Count++) {
|
||||
SetupCommonBuffer(&BdlAddressPointer, sizeof(HDA_BUFFER_DESCRIPTOR_LIST), &BdlMapping, 16);
|
||||
|
||||
BdlAddress = (uint64_t)BdlAddressPointer;
|
||||
WriteValue = (BdlAddress & 0xFFFFFFFF);
|
||||
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_ISSN_OFFSET(Count) + HDA_RELATIVE_OFFSET_SDXBDPL,
|
||||
(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
WriteValue = (BdlAddress >> 32);
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_ISSN_OFFSET(Count) + HDA_RELATIVE_OFFSET_SDXBDPU,
|
||||
(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
}
|
||||
|
||||
for (Count = 0; Count < OssCount; Count++) {
|
||||
SetupCommonBuffer(&BdlAddressPointer, sizeof(HDA_BUFFER_DESCRIPTOR_LIST), &BdlMapping, 16);
|
||||
|
||||
BdlAddress = (uint64_t)BdlAddressPointer;
|
||||
WriteValue = (BdlAddress & 0xFFFFFFFF);
|
||||
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_OSSN_OFFSET(Count, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXBDPL,
|
||||
(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
WriteValue = (BdlAddress >> 32);
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_OSSN_OFFSET(Count, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXBDPU,
|
||||
(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
}
|
||||
|
||||
for (Count = 0; Count < BssCount; Count++) {
|
||||
SetupCommonBuffer(&BdlAddressPointer, sizeof(HDA_BUFFER_DESCRIPTOR_LIST), &BdlMapping, 16);
|
||||
|
||||
BdlAddress = (uint64_t)BdlAddressPointer;
|
||||
WriteValue = (BdlAddress & 0xFFFFFFFF);
|
||||
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_BSSN_OFFSET(Count, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXBDPL,
|
||||
(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
WriteValue = (BdlAddress >> 32);
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, CALCULATE_BSSN_OFFSET(Count, ControllerRegisterSet->GCAP) + HDA_RELATIVE_OFFSET_SDXBDPU,
|
||||
(void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
}
|
||||
|
||||
SetupCommonBuffer(&DmaAddressPointer, (IssCount + OssCount + BssCount) * sizeof(uint64_t), &DmaMapping, 16);
|
||||
DmaAddress = (uint64_t)DmaAddressPointer;
|
||||
|
||||
WriteValue = (DmaAddress & 0xFFFFFFFF);
|
||||
WriteValue |= 0x01;
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_DPIBLBASE, (void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
WriteValue = (DmaAddress >> 32);
|
||||
WriteControllerRegister(PcieDeviceConfigSpace, HDA_OFFSET_DPIBUBASE, (void *)&WriteValue, 1, Bar0, EfiPciWidthUint32);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue