feat/kernel: Did some lapic stuff
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10D1CC0526FDC6D7
7 changed files with 193 additions and 91 deletions
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@ -36,7 +36,7 @@ ifeq ($(BUILD_MODE),release)
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-mno-80387 -mno-mmx -mno-sse -mno-sse2 -mno-red-zone \
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-mcmodel=kernel -fno-unwind-tables -fno-asynchronous-unwind-tables \
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-s -Wno-unused-variable -DBUILD_MODE=\"release\"
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NASMFLAGS :=
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NASMFLAGS := -f elf64 -F dwarf -g
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LDFLAGS := -nostdlib -static -z max-page-size=0x1000 -Wl,--gc-sections \
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-T linker.ld -Wl,-m,elf_x86_64 -Wl,--strip-all
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else
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@ -45,7 +45,7 @@ else
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-ffunction-sections -fdata-sections -m64 -march=x86-64 \
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-mno-80387 -mno-mmx -mno-sse -mno-sse2 -mno-red-zone \
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-mcmodel=kernel -Wno-unused-variable -DBUILD_MODE=\"dev\"
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NASMFLAGS := -F dwarf -g
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NASMFLAGS := -f elf64 -F dwarf -g
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LDFLAGS := -nostdlib -static -z max-page-size=0x1000 -Wl,--gc-sections \
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-T linker.ld -Wl,-m,elf_x86_64
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endif
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@ -10,20 +10,22 @@
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#include <mm/heap.h>
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#include <arch/io.h>
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#include <sys/apic/lapic.h>
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#include <sys/acpi/madt.h>
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#include <arch/paging.h>
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#include <util/align.h>
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#include <mm/pmm.h>
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#define MAX_CPUS 256
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#define MSR_GS_BASE 0xC0000101
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uint32_t cpu_count = 0;
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uint32_t bootstrap_lapic_id = 0;
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atomic_uint started_cpus = 0;
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static cpu_local_t cpu_locals[MAX_CPUS];
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cpu_local_t *get_cpu_local(void)
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{
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cpu_local_t *cpu = (cpu_local_t *)rdmsr(MSR_GS_BASE);
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return cpu;
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return (cpu_local_t *)rdmsr(MSR_GS_BASE);
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}
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static inline void set_cpu_local(cpu_local_t *cpu)
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@ -46,29 +48,32 @@ void smp_entry(struct limine_mp_info *smp_info)
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}
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if (!cpu)
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kpanic(NULL, "CPU with LAPIC ID %u not found in cpu_locals!", lapic_id);
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kpanic(NULL, "CPU with LAPIC ID %u not found!", lapic_id);
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set_cpu_local(cpu);
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atomic_fetch_add(&started_cpus, 1);
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log_early("CPU %d is up", cpu->cpu_index);
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/* Setup core */
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pmset(kernel_pagemap);
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lapic_enable();
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atomic_fetch_add(&started_cpus, 1);
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log_early("CPU %d (LAPIC ID %u) is up", cpu->cpu_index, lapic_id);
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cpu->ready = true;
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while (1)
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__asm__ volatile("hlt");
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hlt();
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}
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void smp_init(void)
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{
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bootstrap_lapic_id = mp_response->bsp_lapic_id;
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cpu_count = mp_response->cpu_count;
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log_early("%u CPUs detected", cpu_count);
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lapic_enable();
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for (uint32_t i = 0; i < cpu_count; i++)
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{
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struct limine_mp_info *info = mp_response->cpus[i];
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memset(&cpu_locals[i], 0, sizeof(cpu_local_t));
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cpu_locals[i].lapic_id = info->lapic_id;
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cpu_locals[i].cpu_index = i;
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@ -77,30 +82,28 @@ void smp_init(void)
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if (info->lapic_id == bootstrap_lapic_id)
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{
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set_cpu_local(&cpu_locals[i]);
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log_early("CPU %u is the bootstrap processor", i);
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atomic_fetch_add(&started_cpus, 1);
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cpu_locals[i].ready = true;
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atomic_fetch_add(&started_cpus, 1);
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log_early("CPU %u (LAPIC ID %u) is the bootstrap processor", i, info->lapic_id);
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}
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else
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{
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__atomic_store_n(&info->goto_address, smp_entry, __ATOMIC_SEQ_CST);
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while (atomic_load(&started_cpus) < (i + 1))
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__asm__ volatile("pause");
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}
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}
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/* trick to wait for all procs to be ready */
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bool all_ready = false;
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while (!all_ready)
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{
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all_ready = true;
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for (uint32_t i = 0; i < cpu_count; i++)
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{
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volatile uint64_t timeout = 0;
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while (!cpu_locals[i].ready)
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{
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__asm__ volatile("pause");
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timeout++;
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}
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if (!cpu_locals[i].ready)
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{
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all_ready = false;
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__asm__ volatile("pause");
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break;
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log_early("warning: CPU %u (LAPIC ID %u) failed to start", i, info->lapic_id);
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}
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else
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{
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log_early("CPU %u (LAPIC ID %u) started successfully", i, info->lapic_id);
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}
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}
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}
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@ -43,6 +43,12 @@ __attribute__((used, section(".limine_requests"))) static volatile struct limine
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__attribute__((used, section(".limine_requests"))) static volatile struct limine_mp_request mp_request = {
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.revision = 0,
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.id = LIMINE_MP_REQUEST};
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__attribute__((used, section(".limine_requests"))) static volatile struct limine_bootloader_info_request binfo_request = {
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.revision = 0,
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.id = LIMINE_BOOTLOADER_INFO_REQUEST};
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__attribute__((used, section(".limine_requests"))) static volatile struct limine_firmware_type_request firmware_request = {
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.revision = 0,
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.id = LIMINE_FIRMWARE_TYPE_REQUEST};
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__attribute__((used, section(".limine_requests_start"))) static volatile LIMINE_REQUESTS_START_MARKER;
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__attribute__((used, section(".limine_requests_end"))) static volatile LIMINE_REQUESTS_END_MARKER;
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@ -87,8 +93,18 @@ void emk_entry(void)
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/* Just do nothing */
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}
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if (!binfo_request.response)
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{
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kpanic(NULL, "Failed to get bootloader info");
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}
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if (!firmware_request.response)
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{
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kpanic(NULL, "Failed to get firmware type");
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}
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log_early("Experimental Micro Kernel (EMK) 1.0 Copyright (c) 2025 Piraterna");
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log_early("Compiled at %s %s, emk1.0-%s, flanterm support: %s", __TIME__, __DATE__, BUILD_MODE, FLANTERM_SUPPORT ? "yes" : "no");
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log_early("Compiled at %s %s, emk1.0-%s, flanterm support: %s, bootloader: %s v%s, firmware: %s", __TIME__, __DATE__, BUILD_MODE, FLANTERM_SUPPORT ? "yes" : "no", binfo_request.response->name, binfo_request.response->version, (firmware_request.response->firmware_type == LIMINE_FIRMWARE_TYPE_UEFI64 || firmware_request.response->firmware_type == LIMINE_FIRMWARE_TYPE_UEFI32) ? "UEFI" : "BIOS");
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log_early("%s", LOG_SEPARATOR);
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if (!LIMINE_BASE_REVISION_SUPPORTED)
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@ -160,15 +176,6 @@ void emk_entry(void)
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*c = 32;
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kfree(c);
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/* Setup SMP */
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if (!mp_request.response)
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{
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kpanic(NULL, "Failed to get MP request");
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}
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mp_response = mp_request.response;
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smp_init();
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/* Setup ACPI */
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rsdp_response = rsdp_request.response;
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if (!rsdp_response)
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@ -182,9 +189,18 @@ void emk_entry(void)
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outb(0x21, 0xff);
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outb(0xA1, 0xff);
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/* Setup APIC */
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/* Init APIC (LAPIC for now) */
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lapic_init();
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/* Setup SMP */
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if (!mp_request.response)
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{
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kpanic(NULL, "Failed to get MP request");
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}
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mp_response = mp_request.response;
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smp_init();
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/* Finished */
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log_early("%s", LOG_SEPARATOR);
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log_early("Finished initializing EMK v1.0, took ? seconds"); /* Still not usermode, so keep using log_early */
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@ -135,6 +135,7 @@ void *vallocat(vctx_t *ctx, size_t pages, uint64_t flags, uint64_t phys)
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vmap(ctx->pagemap, new->start + (i * PAGE_SIZE), page, new->flags);
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}
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memset((void *)new->start, PAGE_SIZE * pages, 0);
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return (void *)new->start;
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}
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region = region->next;
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@ -160,6 +161,7 @@ void *vallocat(vctx_t *ctx, size_t pages, uint64_t flags, uint64_t phys)
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vmap(ctx->pagemap, new->start + (i * PAGE_SIZE), page, new->flags);
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}
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memset((void *)new->start, PAGE_SIZE * pages, 0);
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return (void *)new->start;
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}
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@ -1,14 +1,28 @@
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/* EMK 1.0 Copyright (c) 2025 Piraterna */
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#include <sys/acpi.h>
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#include <boot/emk.h>
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#include <lib/string.h>
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#include <util/log.h>
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#include <sys/kpanic.h>
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#include <mm/vmm.h>
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#include <mm/heap.h>
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static int acpi_uses_xsdt = 0;
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static void *acpi_rsdt_ptr = NULL;
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void *acpi_vtable(uint64_t phys)
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{
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acpi_sdt_header_t *tmp = (acpi_sdt_header_t *)vallocat(kvm_ctx, 1, VALLOC_RW, phys);
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if (!tmp)
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{
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kpanic(NULL, "Failed to map first page of ACPI table");
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return NULL;
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}
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uint32_t full_size = tmp->length;
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uint32_t page_count = (full_size + 0xFFF) / 0x1000;
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return vallocat(kvm_ctx, page_count, VALLOC_RW, phys);
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}
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void acpi_init(void)
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{
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if (!rsdp_response || !rsdp_response->address)
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@ -18,45 +32,52 @@ void acpi_init(void)
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acpi_rsdp_t *rsdp = (acpi_rsdp_t *)vallocat(kvm_ctx, 1, VALLOC_RW, rsdp_response->address);
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if (memcmp(rsdp->signature, "RSD PTR", 7) != 0)
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kpanic(NULL, "Invalid RSDP signature!");
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kpanic(NULL, "Invalid RSDP signature! EMK depends on APIC 1.0 or higher");
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if (rsdp->revision != 0)
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if (rsdp->revision >= 2)
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{
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acpi_uses_xsdt = 1;
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acpi_xsdp_t *xsdp = (acpi_xsdp_t *)rsdp;
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acpi_rsdt_ptr = (acpi_xsdt_t *)HIGHER_HALF(xsdp->xsdt_address);
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log_early("XSDT found at %p", acpi_rsdt_ptr);
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return;
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acpi_rsdt_ptr = acpi_vtable(xsdp->xsdt_address);
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log_early("Using XSDT");
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}
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else
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{
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acpi_uses_xsdt = 0;
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acpi_rsdt_ptr = acpi_vtable(rsdp->rsdt_address);
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log_early("Using RSDT");
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}
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acpi_rsdt_ptr = (acpi_rsdt_t *)HIGHER_HALF(rsdp->rsdt_address);
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log_early("RSDT found at %p", acpi_rsdt_ptr);
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}
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void *acpi_find_table(const char *name)
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{
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if (!acpi_uses_xsdt)
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if (!acpi_rsdt_ptr || !name)
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return NULL;
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if (acpi_uses_xsdt)
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{
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acpi_xsdt_t *xsdt = (acpi_xsdt_t *)acpi_rsdt_ptr;
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uint32_t entries = (xsdt->sdt.length - sizeof(xsdt->sdt)) / 8;
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for (uint32_t i = 0; i < entries; i++)
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{
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uint64_t phys_addr = ((uint64_t *)xsdt->table)[i];
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acpi_sdt_header_t *sdt = (acpi_sdt_header_t *)acpi_vtable(phys_addr);
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if (!memcmp(sdt->signature, name, 4))
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return sdt;
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}
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}
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else
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{
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acpi_rsdt_t *rsdt = (acpi_rsdt_t *)acpi_rsdt_ptr;
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uint32_t entries = (rsdt->sdt.length - sizeof(rsdt->sdt)) / 4;
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for (uint32_t i = 0; i < entries; i++)
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{
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acpi_sdt_header_t *sdt = (acpi_sdt_header_t *)HIGHER_HALF(*((uint32_t *)rsdt->table + i));
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uint32_t phys_addr = ((uint32_t *)rsdt->table)[i];
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acpi_sdt_header_t *sdt = (acpi_sdt_header_t *)acpi_vtable(phys_addr);
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if (!memcmp(sdt->signature, name, 4))
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return (void *)sdt;
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}
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return NULL;
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}
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acpi_xsdt_t *xsdt = (acpi_xsdt_t *)acpi_rsdt_ptr;
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log_early("XSDT address: %p", xsdt);
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uint32_t entries = (xsdt->sdt.length - sizeof(xsdt->sdt)) / 8;
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for (uint32_t i = 0; i < entries; i++)
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{
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acpi_sdt_header_t *sdt = (acpi_sdt_header_t *)HIGHER_HALF(*((uint64_t *)xsdt->table + i));
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if (!memcmp(sdt->signature, name, 4))
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{
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return (void *)sdt;
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return sdt;
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}
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}
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@ -1,43 +1,75 @@
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/* EMK 1.0 Copyright (c) 2025 Piraterna */
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#include <sys/apic/lapic.h>
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#include <arch/cpu.h>
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#include <sys/acpi/madt.h>
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#include <arch/paging.h>
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#include <util/log.h>
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#include <mm/vmm.h>
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#include <stdatomic.h>
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#include <sys/kpanic.h>
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atomic_uintptr_t lapic_msr = 0;
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volatile uint64_t *lapic_base = 0;
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atomic_uintptr_t lapic_base_atomic = 0;
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#define LAPIC_BASE ((volatile uint32_t *)atomic_load(&lapic_base_atomic))
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void lapic_write(uint32_t offset, uint32_t value)
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{
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if (!lapic_base)
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volatile uint32_t *base = LAPIC_BASE;
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if (!base)
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{
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log_early("warning: LAPIC not initialized!");
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return;
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log_early("error: LAPIC not initialized!");
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kpanic(NULL, "LAPIC write attempted before initialization");
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}
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volatile uint32_t *reg = (volatile uint32_t *)((uint8_t *)lapic_base + offset);
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atomic_store((_Atomic uint32_t *)reg, value);
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base[offset / 4] = value;
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}
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uint32_t lapic_read(uint32_t offset)
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{
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if (!lapic_base)
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volatile uint32_t *base = LAPIC_BASE;
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if (!base)
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{
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log_early("warning: LAPIC not initialized!");
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log_early("error: LAPIC not initialized!");
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return 0;
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}
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volatile uint32_t *reg = (volatile uint32_t *)((uint8_t *)lapic_base + offset);
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return atomic_load((_Atomic uint32_t *)reg);
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return base[offset / 4];
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}
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void lapic_init()
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void lapic_init(void)
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{
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uint64_t msr = rdmsr(LAPIC_BASE);
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uint64_t msr = rdmsr(LAPIC_BASE_MSR);
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msr |= (1 << 11); // Set global LAPIC enable bit
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wrmsr(LAPIC_BASE_MSR, msr);
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atomic_store(&lapic_msr, msr);
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lapic_base = (volatile uint64_t *)(msr & ~(0xffff));
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atomic_store(&lapic_addr, (uint64_t)lapic_base);
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log_early("New LAPIC base: 0x%lx", lapic_base);
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uint64_t phys_addr = msr & ~0xFFFULL;
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uint64_t virt_addr = (uint64_t)HIGHER_HALF(phys_addr);
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int ret = vmap(pmget(), virt_addr, phys_addr, VMM_PRESENT | VMM_WRITE | VMM_NX);
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if (ret != 0)
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{
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log_early("error: Failed to map LAPIC base 0x%lx to 0x%lx", phys_addr, virt_addr);
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kpanic(NULL, "LAPIC mapping failed");
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}
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atomic_store(&lapic_base_atomic, virt_addr);
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atomic_store(&lapic_addr, virt_addr);
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}
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void lapic_enable(void)
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{
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volatile uint32_t *base = LAPIC_BASE;
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if (!base)
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{
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log_early("warning: lapic_enable called before lapic_init");
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return;
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}
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uint32_t svr = lapic_read(LAPIC_SVR);
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svr |= (1 << 8); // Enable APIC
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svr &= ~(1 << 9); // Disable focus processor checking
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svr = (svr & ~0xFF) | 0xFF; // Set spurious interrupt vector to 0xFF
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lapic_write(LAPIC_SVR, svr);
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lapic_write(LAPIC_TPR, 0);
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uint32_t id = lapic_read(LAPIC_ID) >> 24;
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log_early("LAPIC enabled and initialized for CPU %u", id);
|
||||
}
|
||||
|
|
@ -4,13 +4,41 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
#define LAPIC_BASE 0x1b
|
||||
#define LAPIC_REGOFF_LAPICID 0x20
|
||||
#define LAPIC_REGOFF_EOI 0xB0
|
||||
#define LAPIC_REGOFF_SPIV 0xF0
|
||||
#define LAPIC_BASE_MSR 0x1B
|
||||
|
||||
// Local APIC Registers
|
||||
#define LAPIC_ID 0x0020 // Local APIC ID
|
||||
#define LAPIC_VER 0x0030 // Local APIC Version
|
||||
#define LAPIC_TPR 0x0080 // Task Priority
|
||||
#define LAPIC_EOI 0x00B0 // End of Interrupt
|
||||
#define LAPIC_SVR 0x00F0 // Spurious Interrupt Vector
|
||||
#define LAPIC_ESR 0x0280 // Error Status
|
||||
#define LAPIC_ICRLO 0x0300 // Interrupt Command (Low)
|
||||
#define LAPIC_ICRHI 0x0310 // Interrupt Command (High)
|
||||
#define LAPIC_TIMER 0x0320 // LVT Timer
|
||||
#define LAPIC_TICR 0x0380 // Timer Initial Count
|
||||
#define LAPIC_TDCR 0x03E0 // Timer Divide Configuration
|
||||
|
||||
// ICR Fields
|
||||
#define ICR_FIXED 0x00000000
|
||||
#define ICR_INIT 0x00000500
|
||||
#define ICR_STARTUP 0x00000600
|
||||
#define ICR_PHYSICAL 0x00000000
|
||||
#define ICR_ASSERT 0x00004000
|
||||
#define ICR_EDGE 0x00000000
|
||||
#define ICR_NO_SHORTHAND 0x00000000
|
||||
#define ICR_SEND_PENDING 0x00001000
|
||||
#define ICR_DESTINATION_SHIFT 24
|
||||
|
||||
// Startup vector address (must be in first 1MB, page-aligned)
|
||||
#define AP_BOOT_ADDRESS 0x8000 // Example: 32KB physical address
|
||||
|
||||
extern volatile uint32_t *lapic_base;
|
||||
extern uint64_t lapic_addr;
|
||||
|
||||
uint32_t lapic_read(uint32_t offset);
|
||||
void lapic_write(uint32_t offset, uint32_t value);
|
||||
void lapic_init();
|
||||
void lapic_init(void);
|
||||
void lapic_enable(void);
|
||||
|
||||
#endif // LAPIC_H
|
||||
Loading…
Add table
Add a link
Reference in a new issue